German Application No. DE 10 2008 054 481 describes an integrated diode array in the form of a sensor, which includes at least one micropatterned diode pixel that has a diode formed in, on or under a diaphragm, the diaphragm being formed above a cavity. The diode is contacted via leads, which are formed at least partially in, on or under the diaphragm, the diode being formed in a polycrystalline semiconductor layer.
International Patent Publication No. WO 2007/147663 describes an infrared sensor having an array of diode pixels, each diode pixel having a monocrystalline region underneath a self-supporting diaphragm.
FIGS. 6a and 6b schematically show vertical cross-sectional views of an example of an integrated diode array for explaining a problem forming a basis of the present invention, FIG. 6b being an enlarged view of detail A in FIG. 6a. 
In FIG. 6a, reference numeral 1 denotes a semiconductor substrate having an upper side O and a lower side U. A plurality of blocks 4a, 4b, of which only two blocks are shown in the view of FIG. 6a, are suspended or anchored at substrate 1, above a cavity 2 situated beneath them in substrate 1. Blocks 4a, 4b are anchored to substrate 1 by oxide ribs (not shown).
Blocks 4a, 4b have a plurality of diodes D1, D2 and D1′, D2′, respectively, which are positioned in a planar manner and are, in the present exemplary embodiment, infrared diodes, the blocks 4a, 4b representing pixels of an infrared sensor device. Blocks 4a, 4b are separated from one another by respective gaps 3.
Blocks 4a, 4b are each made up of a first n-type well 9, which is formed from a corresponding n-type epitaxial layer. A second well 8, which has the p-type of conduction, is provided in first well 9. Diodes D1, D2 and D1′, D2′ are formed inside of p-type well 8, each of these having a well 7 of the n-type of conduction and a doping region 6 of the p-type of conduction embedded in it. Upper side O of substrate 1, as well as blocks 4a, 4b, are covered by an insulating layer 10 of oxide.
For the sake of simplicity, the electrical contacting of diodes D1, D2 and D1′, D2′ is not shown in FIG. 6a. In FIG. 6b, this electrical contacting is partially shown in detail A of FIG. 6a. 
In particular, contacts K1, K2 passing through insulating layer 10 are formed, which contact p-type doping region 6 and n-type well 7 of diode D1. A conductor track LB is shown connected to contact K1, the conductor track terminating in a bonding pad B, which may be contacted from above by a bonding wire that is not shown. A nitride passivation layer 12 is situated above contacts K1, K2 and conductor track LB.
In this example of an integrated diode array, due to light-generated, surface charge carriers (in this case, electrons) between n-type wells 7 of diodes D1, D2 and D1′, D2′, conductive, parasitic MOS channels may form between individual diodes D1, D2 and D1′, D2′ and thereby reduce the sensitivity of the sensor device. The formation of such MOS channels may be counteracted by appropriate gaps between diodes D1, D2 and D1′, D2′. However, this is at the expense of the space occupied by the sensor device and therefore has a restrictive effect on further integration.
The example of the integrated diode array of FIGS. 6a and 6b is produced using a method known per se, in which cavity 2 is initially formed in the substrate, after which the corresponding dopings are provided for regions 6, 7, 8, 9. After that, diodes D1, D2 and D1′, D2′ are electrically contacted, and ultimately, blocks 4a, 4b are separated from one another by a suitable etching process, by which respective gaps 3 are produced between blocks 4a, 4b. 
FIG. 7 shows a schematic vertical cross-sectional view of a further example of an integrated diode array.
In FIG. 7, reference characters D1a, D1a′ denote individual diodes that are formed in blocks 41, 42, respectively. Blocks 41, 42 each contain an n-type well 9′ of the n-type of conduction, in which p-type doping region 6′ and n-type doping region 7′ of specific diode D1a, D1a′ are formed. Since, in this example, each block 41, 42 only contains a single diode D1a and D1a′, no unwanted MOS channels are formed. However, this type of array is even more detrimental with regard to saving space.
FIG. 8 shows a schematic vertical cross-sectional view of another further example of an integrated diode array.
In comparison with FIG. 6a, the example according to FIG. 8 includes n-type doping regions 15 formed between individual diodes D1, D2 and D1′, D2′ of each block 4a, 4b. In their depth, these n-type doping regions 15 extend to n-type well 9 and may therefore prevent unwanted leakage currents. However, such n-type doping regions require space and increase the complexity of the manufacturing method.